آموزش FPGA: در ادامه طراحی پروسسور دستورات مورد نظر آورده میگردد.
mv Rx,Ry Rx ← [Ry]
mvi Rx,#D Rx ← D
add Rx,Ry Rx ← [Rx] + [Ry]
sub Rx,Ry Rx ← [Rx] − [Ry]
دستور اول انتقال یک رجیستر به رجیستر دیگر را نشان می دهد.
دستور دوم انتقال یک عدد به یک رجیستر را نشا ن میدهد.
دستور سوم جمع دو رجیستر ودستور چهارم تفریق دو رجیستر را نشان میدهد.
تعداد کلاکهایی که برای هر دستور لازم است در جدول زیر نشان داده میگردد.
T1 T2 T3
(mv): I0 RYout, RXin, Done
(mvi): I1 DINout, RXin, Done
(add): I2 RXout, Ain RYout, Gin Gout, RXin, Done
,sub): I3 RXout, Ain RYout, Gin Gout, RXin )
ساختار برنامه VHDL که عملیات مورد نظر را انجام می دهد به قرار زیر است
LIBRARY ieee; USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY proc IS
PORT ( DIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Resetn, Clock, Run : IN STD_LOGIC;
Done : BUFFER STD_LOGIC;
BusWires : BUFFER STD_LOGIC_VECTOR(15 DOWNTO 0));
END proc;
ARCHITECTURE Behavior OF proc IS
. . . declare components
. . . declare signals
BEGIN
High <= ’1’;
Clear <= . . .
Tstep: upcount PORT MAP (Clear, Clock, Tstep_Q);
I <= IR(1 TO 3);
decX: dec3to8 PORT MAP (IR(4 TO 6), High, Xreg);
decY: dec3to8 PORT MAP (IR(7 TO 9), High, Yreg);
controlsignals: PROCESS (Tstep_Q, I, Xreg, Yreg)
BEGIN
. . . specify initial values
CASE Tstep_Q IS
WHEN "00" => - - store DIN in IR as long as Tstep_Q = 0
IRin <= ’1’;
WHEN "01" => - - define signals in time step T1
CASE I IS
. . .
END CASE;
WHEN "10" => - - define signals in time step T2
CASE I IS
. . .
END CASE;
WHEN "11" => - - define signals in time step T3
CASE I IS
. . .
END CASE;
END CASE;
END PROCESS;
reg_0: regn PORT MAP (BusWires, Rin(0), Clock, R0);
. . . instantiate other registers and the adder/subtracter unit
. . . define the bus
END Behavior;
Figure 2b. Skeleton VHDL code for the processor.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY upcount IS
PORT ( Clear, Clock : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END upcount;
ARCHITECTURE Behavior OF upcount IS
SIGNAL Count : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
PROCESS (Clock)
BEGIN
IF (Clock’EVENT AND Clock = ’1’) THEN
IF Clear = ’1’ THEN
Count <= "00";
ELSE
Count <= Count + 1;
END IF;
END IF;
END PROCESS;
Q <= Count;
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dec3to8 IS
PORT ( W : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
En : IN STD_LOGIC;
Y : OUT STD_LOGIC_VECTOR(0 TO 7));
END dec3to8;
ARCHITECTURE Behavior OF dec3to8 IS
BEGIN
PROCESS (W, En)
BEGIN
IF En = ’1’ THEN
CASE W IS
WHEN "000" => Y <= "10000000";
WHEN "001" => Y <= "01000000";
WHEN "010" => Y <= "00100000";
WHEN "011" => Y <= "00010000";
WHEN "100" => Y <= "00001000";
WHEN "101" => Y <= "00000100";
WHEN "110" => Y <= "00000010";
WHEN "111" => Y <= "00000001";
END CASE;
ELSE
Y <= "00000000";
END IF;
END PROCESS;
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY regn IS
GENERIC (n : INTEGER := 16);
PORT ( R : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
Rin, Clock : IN STD_LOGIC;
Q : BUFFER STD_LOGIC_VECTOR(n-1 DOWNTO 0));
END regn;
ARCHITECTURE Behavior OF regn IS
BEGIN
PROCESS (Clock)
BEGIN
IF Clock’EVENT AND Clock = ’1’ THEN
IF Rin = ’1’ THEN
Q <= R;
END IF;
END IF;
END PROCESS;
END Behavior;
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